1. Field of the Invention
The present invention relates generally to a field effect transistor, and more particularly, to a field effect transistor applied to a DRAM, and a method of manufacturing thereof.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices is rapidly increasing due to the remarkable spread of information processing apparatus such as computers. Semiconductor memory devices having functionally large scale storage capacity and capable of high speed operation are required. Accordingly, developments in techniques are carried out regarding high density integration, quick response, and high reliability of semiconductor memory devices.
A DRAM is well known as a semiconductor memory device being capable of random input/output of storage information. A DRAM usually comprises a memory cell array including a storage region for storing a plurality of storage information, and a peripheral circuit required for input from and output to an external source. FIG. 6 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 6, a DRAM 50 comprises a memory cell array 51 for storing data signal of storage information, a row-and-column address buffer 52 for receiving external address signals to select memory cells each forming a unit storage circuit, a row decoder 53 and a column decoder 54 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip has a plurality of memory cells arranged in a matrix manner and each for storing unit storage information. A memory cell is generally constituted by one MOS transistor and one capacitor connected thereto. This memory cell is well known as an one-transistor one-capacitor type memory cell. Such memory cells are widely used for large capacity DRAMs because of its simple structure contributing to the improvement in higher integration density of the memory cell array.
FIG. 7 is a sectional view of a memory cell of a conventional DRAM. Referring to FIG. 7, source/drain regions 6 are formed with a predetermined distance therebetween on a P type silicon substrate 1. Gate electrodes 4b and 4c are formed between the pair of source/drain regions 6 with a gate insulating film 5 thereunder. An insulating oxide film 200 is formed to cover gate electrodes 4b and 4c, with side walls 200a and 200b formed at the side walls thereof. A bit line 150 is connected to one of source/drain regions 6 formed between gate electrodes 4b and 4c. An insulating oxide film 210 and side walls 210a and 210b are formed over and at the side walls of bit line 150. A base portion 11a forming a lower electrode of a capacitor storing charge is connected to the other of source/drain regions 6. Base portion 11a and gate electrode 4b are insulated by side wall 200a and insulating oxide film 200. More specifically, the bottom of side wall 210a formed at the side wall of bit line 150 is located over gate electrode 4b. Insulating oxide film 200 becomes lower in height at one end of the region connecting side wall 210a and insulating oxide film 200. This is due to a manufacturing process that will be described later. In a conventional memory cell, insulating oxide film 200 over gate electrode 4b has a thick portion and a thin portion with a step at the boundary region.
FIGS. 8A-8D are sectional views of the memory cell of the conventional DRAM of FIG. 7. The manufacturing process will be described with reference to FIGS. 7-8D. Referring to FIG. 8A, gate electrodes 4b and 4c are spaced apart on P type silicon substrate 1 with gate insulating film 5 thereunder. Insulating oxide film 200 is formed to cover gate electrodes 4b and 4c. Source/drain regions 6 are formed, followed by forming side walls 200a and 200b to cover the side walls of gate electrodes 4b and 4c, and insulating oxide film 200. Referring to FIG. 8B, bit line 150 is formed to connect one of source/drain regions 6 on P type silicon substrate 1 between gate electrodes 4b and 4c. Side wall 200b and insulating oxide film 200 are interposed between gate electrodes 4b, 4c and bit line 150 to establish withstanding voltage. An insulating oxide film 210 is formed on bit line 150. Referring to FIG. 8C, an oxide film 30 is formed on the whole surface. Referring to FIG. 8D, oxide film 30 is etched anisotropically to form side walls 210a. In forming side walls 210a, a portion of insulating oxide film 200 formed on gate electrodes 4b and 4c is over-etched. This over-etching results in a disadvantage that the thickness of a portion of insulating oxide film 200 is reduced. When base portion 11a connected to source drain region 6 is formed to contact side wall 200a, insulating oxide film 200, side wall 210a and insulating oxide film 210 in the above described state, insulating oxide film 200 interposed between base portion 11a and gate electrode 4b becomes thinner at the portion where oxide film 200 on gate electrode 4b is over-etched. When a portion of insulating oxide film 200 is over-etched to become thinner at that portion due to over-etching in forming side wall 210a, an edge portion is formed at the boundary of the thinner portion and the remaining portion of insulating oxide film 200.
As mentioned above, a memory cell of a conventional DRAM has insulating oxide film 200 on gate electrode 4b over-etched in forming side wall 210a for establishing withstanding voltage between base line 150 and base portion 11a constituting the lower electrode of the capacitor. This will result in a configuration where the thickness of insulating oxide film 200 becomes thinner in the over-etched portion, with an edge portion formed at the boundary of the thick and thin film. This posed a problem that withstanding voltage characteristic between base portion 11a and gate electrode 4b is deteriorated. There was another problem that field concentration occurs at the above-mentioned edge portion.
Conventional semiconductor devices with a multilayer wiring structure scaled to higher densities had a problem that the thickness of the insulating layer interposed between multilayer interconnection layers becomes thin to make it difficult to improve withstanding voltage.